Serial Peripheral Interface Bus or SPI is a synchronous serial data link that operates in either a full or a half-duplex mode. Devices communicate in master-slave fashion, in which the master initiates the data transmission by using a set of signal line interface. A typical SPI includes a serial clock line (“SCLK”), which is sent from the master to all slaves. It also includes a chip select signal (“CS”) line for selecting the slave the master communicates with. Further, most modern SPIs use two data lines, a master-out-slave-in line (“MOSI”) and a master-in-slave-out line (“MISO”), for the full duplex data communication between the master and slaves.
SPI is a single-master communication protocol. At the basic level, a system linked in a typical SPI includes a single master and a single slave, in which the devices communicate in a point-to-point topology. The master initiates SPI transactions by activating the clock signal at a clock frequency usable by both the master and the slave. The master provides data on the MOSI line while it samples data on the MISO line. In a more complex system having multiple slaves, however, additional hardware mechanisms or software protocols are needed for the master to communicate with a specific slave within a group of linked slaves. For instance, the master uses a global SCLK line and one global data line such as MOSI line to command all slaves. The master allots an independent CS line to each of the slaves to activate the slave it wants to communicate with, thereby creating a point-to-multipoint topology. In this SPI configuration, the SCLK line and the data line are shared among all slaves, but only the slave with its CS signal active will acknowledge and respond to the master's command.
This classic SPI configuration, however, comes with a number of problems. First, the number of slave devices that can connect to the master device is limited to the number of CS outputs available at the master. Each additional slave adds to the cost and layout complexity of the system. Second, because the global SCLK line is distributed from the master to all slaves, the capacitive load on the master's SPI port increases with each additional slave in the system. The increase in the capacitive load creates various electrical issues, such as noise and skew on the signal, which negatively affects the overall system stability.
Attempts have been made to solve some of the problems described above. For example, a daisy-chain configuration has been used to minimize the number of CS outputs on the master. In the conventional SPI daisy-chain configuration, the data output of each slave is connected to the data input of the next device in the chain, and the final slave data output is connected to the MISO line on the master. On each group of clock pulses, the SPI port on each slave forwards an exact copy of data received from the preceding device to the next device in the chain, thereby forming a logical shift register. The classic daisy-chain SPI configuration uses only a single CS line from the master to control all slaves. The master outputs a series of commands in a specific order to configure the slaves in the chain, and all slaves in the chain execute the commands written on them upon assertion of the CS signal.
In this classic daisy-chain configuration, the total number of slaves is no longer limited to a finite set of CS outputs on a master. This configuration, however, still operates with a global clock line distributed from the master to all slaves. Not only did the classic daisy-chain SPI configuration fail to solve the excessive capacitive load problem, it introduced a new problem: the SPI interface does not permit any wait states. Since all slaves are connected to the same CS line, all slaves respond to the master command, acting as a large shift register. All slaves in the chain operate as a single device, and each SPI transaction involves every slave in the chain. In other words, the slaves must accept or return data on every clock edge so long as the master is clocking the SPI clock. Accordingly, the standard SPI daisy-chain configuration cannot be used when the slaves require a variable delay before responding to a command.
It would be highly desirable to have an improved serial peripheral interface that does not suffer from the capacitive load problem regardless of the number of slaves in the chain. It would also be desirable to have an improved serial peripheral interface that provides a wait-state functionality, so that the slaves can take a variable number of clock cycles before respond to the master's command. Such SPI configuration would provide a truly flexible and reliable inter-chip data communication interface.